Magnetic memories, particularly magnetic random access memories (MRAMs), have drawn increasing interest due to their potential for high read/write speed, excellent endurance, non-volatility and low power consumption during operation. An MRAM can store information utilizing magnetic materials as an information recording medium. One type of MRAM is a spin transfer torque random access memory (STT-RAM). STT-RAM utilizes magnetic junctions written at least in part by a current driven through the magnetic junction. A spin polarized current driven through the magnetic junction exerts a spin torque on the magnetic moments in the magnetic junction. As a result, layer(s) having magnetic moments that are responsive to the spin torque may be switched to a desired state.
For example, FIG. 1 depicts a conventional magnetic tunneling junction (MTJ) 10 as it may be used in a conventional STT-RAM. The conventional MTJ 10 typically resides on a bottom contact 11, uses conventional seed layer(s) 12 and includes a conventional antiferromagnetic (AFM) layer 14, a conventional pinned layer 16, a conventional tunneling barrier layer 18, a conventional free layer 20, and a conventional capping layer 22. Also shown is top contact 24.
Conventional contacts 11 and 24 are used in driving the current in a current-perpendicular-to-plane (CPP) direction, or along the z-axis as shown in FIG. 1. The conventional seed layer(s) 12 are typically utilized to aid in the growth of subsequent layers, such as the AFM layer 14, having a desired crystal structure. The conventional tunneling barrier layer 18 is nonmagnetic and is, for example, a thin insulator such as MgO.
The conventional pinned layer 16 and the conventional free layer 20 are magnetic. The magnetization 17 of the conventional pinned layer 16 is fixed, or pinned, in a particular direction, typically by an exchange-bias interaction with the AFM layer 14. Although depicted as a simple (single) layer, the conventional pinned layer 16 may include multiple layers. For example, the conventional pinned layer 16 may be a synthetic antiferromagnetic (SAF) layer including magnetic layers antiferromagnetically coupled through thin conductive layers, such as Ru. In such a SAF, multiple magnetic layers interleaved with a thin layer of Ru may be used. In another embodiment, the coupling across the Ru layers can be ferromagnetic. Further, other versions of the conventional MTJ 10 might include an additional pinned layer (not shown) separated from the free layer 20 by an additional nonmagnetic barrier or conductive layer (not shown).
The conventional free layer 20 has a changeable magnetization 21. Although depicted as a simple layer, the conventional free layer 20 may also include multiple layers. For example, the conventional free layer 20 may be a synthetic layer including magnetic layers antiferromagnetically or ferromagnetically coupled through thin conductive layers, such as Ru. Although shown as in-plane, the magnetization 21 of the conventional free layer 20 may have a perpendicular anisotropy.
To switch the magnetization 21 of the conventional free layer 20, a current is driven perpendicular to plane (in the z-direction). When a sufficient current is driven from the top contact 24 to the bottom contact 11, the magnetization 21 of the conventional free layer 20 may switch to be parallel to the magnetization 17 of the conventional pinned layer 16. When a sufficient current is driven from the bottom contact 11 to the top contact 24, the magnetization 21 of the free layer may switch to be antiparallel to that of the pinned layer 16. The differences in magnetic configurations correspond to different magnetoresistances and thus different logical states (e.g. a logical “0” and a logical “1”) of the conventional MTJ 10.
When used in STT-RAM applications, the free layer 21 of the conventional MTJ 10 is desired to be switched at a relatively low current. The critical switching current (Ic0) is the lowest current at which the infinitesimal precession of free layer magnetization 21 around the equilibrium orientation becomes unstable. For example, Ic0 may be desired to be on the order of a few mA or less. In addition, a short current pulse is desired to be used in programming the conventional magnetic element 10 at higher data rates. For example, current pulses on the order of 20-30 ns or less are desired.
Although the conventional MTJ 10 may be written using spin transfer and used in an STT-RAM, there are drawbacks. For example, the write error rates may be higher than desired for memories having an acceptable Ic0 and pulse width. The write error rate (WER) is the probability that a cell (i.e. the magnetization 21 of free layer 20 of the conventional magnetic junction) is not switched when subjected to a current that is at least equal to the typical switching current. The WER is desired to be 10−9 or less. However, the conventional free layer 20 typically has a WER greatly in excess of this value. In addition, it has been determined that the WER may be challenging to improve for shorter write current pulses. For example, FIG. 2 is a graph 50 depicts trends in WERs for pulses of different widths. Note that actual data are not plotted in the graph 50. Instead, the graph 50 is meant to indicate trends. The pulse width, from longest to shortest, is for curves 52, 54, 56, and 58. As can be seen in the graph 50, for higher pulse widths, the WER versus write current has a higher slope. Thus, application of a higher write current for the same pulse width may bring about a significant reduction in the WER. However, as the pulse widths shorten in curves 54, 56, and 58, the slope of the curves 54, 56, and 58 decreases. For a decreasing pulse width, an increase in current is less likely to bring about a reduction in the WER. Consequently, memories employing the conventional MTJ 10 may have unacceptably high WER that may not be cured by an increase in write current.
Various conventional solutions have been proposed to improve characteristics such as the WER. For example, magnetic field assisted switching and/or a magnetic junction having a complex structure may be used. However, the ability of such conventional schemes to reduce the WER while preserving other characteristics is limited. For example, scalability, energy consumption, and/or thermal stability may be adversely affected by such conventional methods. Thus, performance of a memory using the conventional MTJ is still desired to be improved.
Accordingly, what is needed is a method and system that may improve the performance of the spin transfer torque based memories. The method and system described herein address such a need.